DRAM (Dynamic Random Access Memory) technology will eventually scale down to less than 20 nm feature size, leading to a decrease in memory cell capacitance and an increase in cell transistor leakage. The probability distribution of memory cell retention in system memory may be modeled by a normal distribution, but decreasing the feature size does not necessarily tighten the normal distribution, that is, the distribution will continue to exhibit tails with cells having a significantly reduced cell retention compared to the mean cell retention associated with the distribution.
Conventional techniques to address reduced cell retention include increasing the frequency of refresh operations. However, increasing the refresh frequency adversely impacts the available memory bandwidth and leads to an increase in standby power consumption. Alternatively, another conventional technique to address the issue of reduced cell retention is to employ an error recovery scheme such as block error correction (of codewords) used along with a refresh operation to read-correct-write the stored data. However, multiple-bit errors may occur within a codeword. Furthermore, multiple-bit error correction may adversely impact the DRAM die area.